1. Field of the Invention
The present invention relates to a semiconductor device having an integrated circuit and a method for manufacturing the same. The invention particularly relates to an electronic device having, as a component, a semiconductor element including an embedded wiring.
Note that a semiconductor device in this specification means general devices and apparatuses which can function with the use of semiconductor characteristics; for example, electro-optical devices, semiconductor circuits, and electronic devices are all included in a semiconductor device.
2. Description of the Related Art
In recent years, in the case of forming a multilevel interconnection which includes a plurality of wiring layer in a semiconductor element, irregularities are more significant in upper layers, and the wirings are difficult to be processed. Correspondingly, a wiring material is generally embedded in a wiring opening such as a wiring trench or a hole formed in an insulating film by a wiring formation technology called a damascene process.
A damascene process is a method in which a trench is first formed in an insulating film, the entire surface is covered with a metal material (filling the trench), and the entire surface is polished by CMP (chemical mechanical polishing) or the like to form a metal wiring. The method further including a step of providing a hole below a metal wiring for contact with a metal wiring or a semiconductor region in a lower layer is called a dual damascene process. The dual damascene process includes a step in which, after forming a hole for a connection with a lower layer wiring and a wiring trench are formed, a wiring material is deposited, and the wiring material except the wiring part is removed by CMP.
For a metal wiring using a dual damascene process, copper (Cu) by electroplating is commonly used. In the electroplating, a plating solution or the electric field to be applied is required to be controlled intricately so that copper (Cu) is completely embedded in the connection hole. Further, it is difficult to process copper (Cu) by an etching process using an etchant or an etching gas; therefore, a special CMP method is required for polishing for copper (Cu) processing.
Electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring.
Further, in order to achieve a high performance semiconductor device that is capable of high speed operation, a structure in which an insulating film having lower dielectric constant is used for the insulating film to be provided with a wiring opening in addition to using a wiring material having lower resistivity than copper (Cu) is further required in the future.
Hence, the present inventors consider using silver nanoparticles for obtaining a wiring formed of silver or an alloy mainly containing silver each having lower resistivity than copper. However, the present inventors found problems that, since a silicon dioxide film or a silicon nitride film which is used for a conventional interlayer insulating film is dense, the area in contact with silver nanoparticles is small and the adhesion is weak.
Further, as for a silicon dioxide film (∈=4.1 to 3.7) which has been used for a conventional interlayer insulating film, the dielectric constant is high; thus, an insulating film having further lower dielectric constant is required.